Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity

TL;DR

This paper introduces a test architecture for array multipliers that achieves high fault coverage with minimal hardware overhead by combining C-testability, bijectivity, and deterministic test pattern generation.

Contribution

It proposes a scalable, low-overhead test architecture for array multipliers that requires only five test vectors and integrates multiple testability techniques.

Findings

100% fault coverage for single stuck-at faults

Less than 0.5% area and delay overhead for 64-bit multipliers

Requires only five test vectors regardless of multiplier size

Abstract

This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100% fault coverage for single stuck-at faults. The proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5% for a 64-bit multiplier.