High-level Synthesis using the Julia Language

TL;DR

This paper introduces a Julia-based High-level Synthesis tool that simplifies hardware accelerator design by leveraging Julia's readability and existing libraries, transforming Julia code into VHDL.

Contribution

It presents a novel Julia HLS tool that reduces the complexity of hardware design and demonstrates how Julia's features facilitate HLS development.

Findings

Prototype Julia HLS tool successfully transforms Julia code into VHDL.

Julia's language features simplify the creation of HLS tools.

The approach lowers the barrier to entry for hardware acceleration.

Abstract

The growing proliferation of FPGAs and High-level Synthesis (HLS) tools has led to a large interest in designing hardware accelerators for complex operations and algorithms. However, existing HLS toolflows typically require a significant amount of user knowledge or training to be effective in both industrial and research applications. In this paper, we propose using the Julia language as the basis for an HLS tool. The Julia HLS tool aims to decrease the barrier to entry for hardware acceleration by taking advantage of the readability of the Julia language and by allowing the use of the existing large library of standard mathematical functions written in Julia. We present a prototype Julia HLS tool, written in Julia, that transforms Julia code to VHDL. We highlight how features of Julia and its compiler simplified the creation of this tool, and we discuss potential directions for future work.