A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS

TL;DR

This paper presents a high-speed, low-power 8-bit pipelined-SAR ADC in 14nm CMOS using a novel output level shifting technique to improve settling time and enable low-voltage operation.

Contribution

It introduces an output level shifting settling technique that reduces power and settling time, allowing for high-speed operation in a compact 14nm CMOS implementation.

Findings

Achieves 1.5GS/s sampling rate with 6.6-bit ENOB at Nyquist.

Consumes 2.4mW power with an FOM of 16.7fJ/conv.-step.

Uses a novel OLS technique to reduce settling time to 28% of conventional methods.

Abstract

A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage and a 5-bit second stage, with 1-bit redundancy to relax the offset, gain, and settling requirements of the first stage. Employing the OLS technique allows for an inter-stage gain of ~4 from the dynamic residue amplifier with a settling time that is only 28% of a conventional CML amplifier. The ADC's conversion speed is further improved with the use of parallel comparators in the two asynchronous stages. Fabricated in a 14nm FinFET technology, the ADC occupies 0.0013mm2 core area and operates with a 0.8V supply. 6.6-bit ENOB is achieved at Nyquist while consuming 2.4mW, resulting in an FOM of 16.7fJ/conv.-step.