FPGA-based real-time data processing for accelerating reconstruction at LHCb

TL;DR

This paper discusses the development of FPGA-based real-time data processing hardware to accelerate event reconstruction in the LHCb experiment during Run-3, enabling high-speed processing at 30 MHz.

Contribution

It introduces a novel FPGA-implemented tracking processor prototype designed for real-time event reconstruction in high-energy physics experiments.

Findings

Prototype successfully processes real data during Run-3

Achieves high parallelization with FPGA technology

Demonstrates feasibility for future high-luminosity runs

Abstract

In Run-3, beginning in 2022, the LHCb software trigger will start reconstructing events at the LHC average crossing rate of 30 MHz. Within the upgraded DAQ system, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction, in view of future runs at even higher luminosities. One such solution is a highly-parallelized custom tracking processor ("Artificial Retina"), implemented in state of the art FPGA devices connected by fast serial links. We describe the status of a realistic prototype for the reconstruction of pixel tracking detectors that will run on real data during Run-3.