Hardware-Efficient Deconvolution-Based GAN for Edge Computing

TL;DR

This paper introduces a hardware-efficient FPGA-based accelerator for quantized deconvolution GANs, enabling high-throughput, low-power edge computing with an open-source framework for training and deployment.

Contribution

It presents a scalable FPGA architecture for deconvolution GANs with optimized deconvolution engine and an open-source framework for training and inference.

Findings

Achieved higher throughput with efficient resource utilization.

Supported multiple precisions and network scales for low-power inference.

Provided a comprehensive open-source toolchain for FPGA deployment.

Abstract

Generative Adversarial Networks (GAN) are cutting-edge algorithms for generating new data samples based on the learned data distribution. However, its performance comes at a significant cost in terms of computation and memory requirements. In this paper, we proposed an HW/SW co-design approach for training quantized deconvolution GAN (QDCGAN) implemented on FPGA using a scalable streaming dataflow architecture capable of achieving higher throughput versus resource utilization trade-off. The developed accelerator is based on an efficient deconvolution engine that offers high parallelism with respect to scaling factors for GAN-based edge computing. Furthermore, various precisions, datasets, and network scalability were analyzed for low-power inference on resource-constrained platforms. Lastly, an end-to-end open-source framework is provided for training, implementation, state-space exploration, and scaling the inference using Vivado high-level synthesis for Xilinx SoC-FPGAs, and a comparison testbed with Jetson Nano.