VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

TL;DR

This paper introduces VAR-DRAM, a variation-aware framework that improves energy efficiency and performance in DRAM by modeling variations and remapping data, achieving significant energy savings and latency improvements.

Contribution

It presents a novel variation-aware DRAM framework that enhances power management, data reliability, and access speed by accounting for process, voltage, and temperature variations.

Findings

Up to 48.8% energy savings with VAR-DRAM

Average of 29.54% energy reduction on DDR4

7.4% improvement in access latency

Abstract

Dynamic Random Access Memory (DRAM) is the de-facto choice for main memory devices due to its cost-effectiveness. It offers a larger capacity and higher bandwidth compared to SRAM but is slower than the latter. With each passing generation, DRAMs are becoming denser. One of its side-effects is the deviation of nominal parameters: process, voltage, and temperature. DRAMs are often considered as the bottleneck of the system as it trades off performance with capacity. With such inherent limitations, further deviation from nominal specifications is undesired. In this paper, we investigate the impact of variations in conventional DRAM devices on the aspects of performance, reliability, and energy requirements. Based on this study, we model a variation-aware framework, called VAR-DRAM, targeted for modern-day DRAM devices. It provides enhanced power management by taking variations into account. VAR-DRAM ensures faster execution of programs as it internally remaps data from variation affected cells to normal cells and also ensures data preservation. On extensive experimentation, we find that VAR-DRAM achieves peak energy savings of up to 48.8% with an average of 29.54% on DDR4 memories while improving the access latency of the DRAM compared to a variation affected device by 7.4%.