PdSe2 based field-effect transistors

TL;DR

This study uses multi-scale simulation to evaluate PdSe2 monolayer p-type FETs, revealing excellent switching, good current, and scalability down to 7 nm, with performance trade-offs below that.

Contribution

It provides a detailed analysis of PdSe2 monolayer FET performance and scalability using combined DFT and quantum transport simulations, highlighting optimal device dimensions.

Findings

Excellent sub-65 mV/decade switching performance

Scalability down to 7 nm channel length without performance loss

Degradation below 7 nm can be mitigated by underlap design

Abstract

Pentagonal PdSe2 is a promising candidate for layered electronic devices, owing to its high air-stability and anisotropic transport properties. Here, we investigate the performance of p-type FET based on PdSe$_2$ mono-layer using multi-scale simulation framework combining Density functional theory and quantum transport. We find that mono-layer PdSe$_2$ devices show excellent switching characteristics ($<$ 65 mV/decade) for the source-drain direction aligned along both [010] and [100] directions. Both directions also show good on-state current and large transconductance, though these are larger along the [010] direction for a 15 nm channel device. The channel length scaling study of these p-FETs indicates that channel length can be easily scaled down to 7 nm without any significance compromise in the performance. Going below 7 nm, we find that there is a severe degradation in the sub-threshold swing for 4 nm channel length. However, this degradation can be minimized by introducing an underlap structure. The length of underlap is determined by the trade-off between on-state current and the switching performance.