Configurable Independent Component Analysis Preprocessing Accelerator

TL;DR

This paper introduces a high-throughput, configurable hardware accelerator for ICA preprocessing, utilizing a novel matrix multiplication array and parallel pipelined processing to significantly enhance efficiency.

Contribution

It presents a new hardware architecture for ICA preprocessing that combines a high-performance MMA with parallel processing, improving throughput and hardware utilization.

Findings

Achieves 40.7k matrices/sec throughput

Uses time-multiplexed MMA architecture

Provides detailed circuit design and performance estimates

Abstract

Independent component analysis (ICA) has been used in many applications, including self-interference cancellation for in-band full-duplex wireless systems and anomaly detection in industrial internet of things. This paper presents a high-throughput and highly efficient configurable preprocessing accelerator for the ICA algorithm. The proposed ICA accelerator has three major blocks that perform data centering, covariance matrix for computation, and eigenvalue decomposition (EVD). Specifically, the proposed accelerator is based on a high-performance matrix multiplication array (MMA). The proposed MMA architecture uses time-multiplexed processing so that the efficiency of hardware utilization is greatly enhanced. Furthermore, the processing flow utilizes parallel processing such that the centering, the calculation of the covariance matrix, and EVD are conducted simultaneously and are individually pipelined to maximize throughput. This paper presents the architecture, circuit design, and performance estimates based on post-layout extraction of the proposed preprocessing ICA accelerator. The proposed design achieves a throughput of 40.7 kMatrices per second at complexity of 73.3 kGE.