Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

TL;DR

This paper proposes a scalable silicon quantum processor architecture with sparse 2D connectivity, optimized compilation strategies, and CMOS manufacturability, enabling efficient quantum operations and improved scalability over existing methods.

Contribution

It introduces a novel modular 2D spin-qubit architecture with optimized compilation strategies that outperform existing methods, suitable for CMOS fabrication.

Findings

Outperforms best-in-class 1D compilation strategies.

Allows scalable 2D quantum processor design.

Compatible with CMOS fabrication processes.

Abstract

Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardware elements, we propose a modular sparse 2d spin-qubit architecture with unit cells consisting of diagonally-oriented squares with nanowires along the edges and junctions on the corners. We show that this architecture allows for compilation strategies which outperform the best-in-class compilation strategy for 1d chains, not only asymptotically, but also down to the minimal structure of a single square. The proposed architecture exhibits favorable scaling properties which allow for balancing the trade-off between compilation overhead and co-location of classical control electronics within each square by adjusting the length of the nanowires. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes. Finally, we note that our compilation strategies, while being inspired by spin-qubits, are equally valid for any other quantum processor with sparse 2d connectivity.