Scaling Quantum Approximate Optimization on Near-term Hardware

TL;DR

This paper analyzes how the resource requirements of the QAOA algorithm scale with problem size and hardware limitations, highlighting exponential growth in measurements needed under realistic noisy conditions.

Contribution

It provides a quantitative analysis of QAOA resource scaling on near-term hardware, considering noise, connectivity, and circuit depth, and discusses potential mitigation strategies.

Findings

Measurement count grows exponentially with problem size and graph degree.

Higher hardware connectivity can reduce resource requirements.

Modifications to QAOA can improve performance with fewer layers.

Abstract

The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.