ADRA: Extending Digital Computing-in-Memory with Asymmetric Dual-Row-Activation
Akul Malhotra, Atanu K. Saha, Chunguang Wang, Sumeet K. Gupta

TL;DR
This paper introduces ADRA, a novel digital computing-in-memory technique using asymmetric dual-row-activation, enabling efficient computation of a broader class of functions including non-commutative operations like subtraction, with significant energy-delay improvements.
Contribution
It proposes an asymmetric wordline biasing scheme that allows single-cycle memory read and computation of all Boolean functions, extending CiM capabilities to non-commutative operations.
Findings
Enables simultaneous single-cycle memory read and Boolean function computation.
Supports computation of non-commutative functions like subtraction.
Achieves 23.2% - 72.6% reduction in energy-delay product compared to standard methods.
Abstract
Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wordline assertion for computing bit-wise Boolean functions and arithmetic functions such as addition. However, most of these techniques, due to the many-to-one mapping of input vectors to bitline voltages, are limited to CiM of commutative functions, leaving out an important class of computations such as subtraction. In this paper, we propose a CiM approach, which solves the mapping problem through an asymmetric wordline biasing scheme, enabling (a) simultaneous single-cycle memory read and CiM of primitive Boolean functions (b) computation of any Boolean function and (c) CiM of non-commutative functions such as subtraction and comparison. While the proposed technique is technology-agnostic, we show its utility…
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Taxonomy
TopicsFerroelectric and Negative Capacitance Devices · Semiconductor materials and devices · Advanced Memory and Neural Computing
