A Priority-Aware Multiqueue NIC Design

TL;DR

This paper introduces a priority-aware NIC design that reduces network interrupts and processing delays in real-time embedded systems, improving responsiveness in industrial and autonomous applications.

Contribution

It proposes a novel NIC architecture that maps IP flows to processes and applies priority-based interrupt moderation, enhancing real-time performance.

Findings

93% of interrupts can be saved

80% decrease in processing delay of critical tasks

Effective in industrial and autonomous system scenarios

Abstract

Low-level embedded systems are used to control cyber-phyiscal systems in industrial and autonomous applications. They need to meet hard real-time requirements as unanticipated controller delays on moving machines can have devastating effects. Modern developments such as the industrial Internet of Things and autonomous machines require these devices to connect to large IP networks. Since Network Interface Controllers (NICs) trigger interrupts for incoming packets, real-time embedded systems are subject to unpredictable preemptions when connected to such networks. In this work, we propose a priority-aware NIC design to moderate network-generated interrupts by mapping IP flows to processes and based on that, consolidates their packets into different queues. These queues apply priority-dependent interrupt moderation. First experimental evaluations show that 93% of interrupts can be saved leading to an 80% decrease of processing delay of critical tasks in the configurations investigated.