Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores
Rakesh Kumar, Mehdi Alipour, and David Black-Schaffer

TL;DR
This paper introduces Freeway, a dependence-aware slice-out-of-order core that significantly improves memory level parallelism and performance efficiency while maintaining low energy overheads, bridging the gap with traditional out-of-order cores.
Contribution
The paper proposes a novel dependence-aware slice execution policy for sOoO cores, enhancing MLP exploitation and performance with minimal hardware overhead.
Findings
Freeway achieves 12% better performance than existing sOoO cores.
It approaches the MLP benefits of full OoO cores, within 7%.
Minimal area and power overheads are incurred.
Abstract
Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are effective at exploiting MLP, they deliver poor energy efficiency due to their complex and energy-hungry hardware. This work revisits slice-out-of-order (sOoO) cores as an energy efficient alternative for MLP exploitation. sOoO cores achieve energy efficiency by constructing and executing \textit{slices} of MLP generating instructions out-of-order only with respect to the rest of instructions; the slices and the remaining instructions, by themselves, execute in-order. However, we observe that existing sOoO cores miss significant MLP opportunities due to their dependence-oblivious in-order slice execution, which causes dependent slices to frequently block MLP generation. To boost MLP generation, we introduce…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Memory and Neural Computing · Advanced Data Storage Technologies
