Comparing different solutions for testing resistive defects in low-power SRAMs
Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore, Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda

TL;DR
This paper evaluates various testing methods for resistive defects in low-power SRAMs, highlighting their effectiveness, complexity, and test duration to improve defect detection in manufacturing.
Contribution
It introduces a comparative analysis of testing solutions specifically targeting resistive defects in low-power SRAMs, addressing detection challenges not covered by traditional methods.
Findings
Different testing methods vary in complexity and test time
Some methods are more effective at detecting subtle resistive defects
The analysis guides selecting suitable testing approaches for manufacturing
Abstract
Low-power SRAM architectures are especially sensitive to many types of defects that may occur during manufacturing. Among these, resistive defects can appear. This paper analyzes some types of such defects that may impair the device functionalities in subtle ways, depending on the defect characteristics, and that may not be directly or easily detectable by traditional test methods, such as March algorithms. We analyze different methods to test such defects and discuss them in terms of complexity and test time.
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Advancements in Photolithography Techniques
