Understanding Hot Carrier Reliability in FinFET Technology from Trap-based Approach

TL;DR

This paper investigates hot carrier degradation in FinFETs using a trap-based approach, combining experimental and simulation methods to develop a predictive model for device reliability under various stress conditions.

Contribution

It introduces a unified compact model for hot carrier degradation that incorporates interface and oxide traps, validated by experiments and simulations.

Findings

Two types of oxide traps identified as contributors to HCD

The unified model accurately predicts degradation under different bias conditions

Temperature dependence and trap locations are thoroughly analyzed

Abstract

In this paper, the recent advances of our studies on hot carrier degradation (HCD) are presented from trap-based approach. The microscopic speculation of interface trap generation is carried out by time-dependent DFT (TDDFT) simulation in "real-time". Two types of oxide traps contributing to HCD are identified from experiments. Combining the contributions of interface and oxide traps, a unified compact model has been proposed which can accurately predict hot carrier degradation and variation in full Vgs/Vds bias. The trap locations, degradation contributions and temperature dependence are studied in detail. In addition, the mixed mode reliability of HCD-BTI coupling through self-heating and under off-state stress are discussed.