Study of neutron irradiation effects in Depleted CMOS detector structures

TL;DR

This study investigates how neutron irradiation affects the electrical properties of Depleted CMOS detectors fabricated in a 150 nm HV-CMOS process, focusing on depletion depth, space charge concentration, and annealing effects.

Contribution

It provides experimental data on neutron irradiation effects in Depleted CMOS structures, including measurements of depletion depth and space charge concentration over a range of fluences and annealing conditions.

Findings

Depletion depth decreases with neutron fluence.

Effective space charge concentration increases with fluence and depends on initial resistivity.

Long-term annealing reduces detector current and stabilizes space charge effects.

Abstract

In this paper results of Edge-TCT and I-V measurements with passive test structures made in LFoundry 150 nm HV-CMOS process on p-type substrates with different initial resistivities ranging from 0.5 to 3 k$\Omega$cm are presented. Samples were irradiated with reactor neutrons up to a fluence of 2$\cdot$10$^{15}$ n$_{\mathrm{eq}}$/cm$^2$. Depletion depth was measured with Edge-TCT. Effective space charge concentration $N_{\mathrm{eff}}$ was estimated from the dependence of depletion depth on bias voltage and studied as a function of neutron fluence. Dependence of $N_{\mathrm{eff}}$ on fluence changes with initial acceptor concentration in agreement with other measurements with p-type silicon. Long term accelerated annealing study of $N_{\mathrm{eff}}$ and detector current up to 1280 minutes at 60$^\circ$C was made. It was found that $N_{\mathrm{eff}}$ and current in reverse biased detector behaves as expected for irradiated silicon.