Implementation of a Binary Neural Network on a Passive Array of Magnetic Tunnel Junctions

TL;DR

This paper demonstrates energy-efficient neural network inference using passive arrays of magnetic tunnel junctions, achieving near-software accuracy despite hardware imperfections through parameter tuning.

Contribution

It introduces a hardware implementation of binary neural networks with MTJs, addressing device variability and demonstrating high accuracy in practical inference tasks.

Findings

Achieved up to 95.3% accuracy on the Wine dataset

Demonstrated robustness to device imperfections through parameter tuning

Validated the feasibility of MTJ-based neural network hardware

Abstract

The increasing scale of neural networks and their growing application space have produced demand for more energy- and memory-efficient artificial-intelligence-specific hardware. Avenues to mitigate the main issue, the von Neumann bottleneck, include in-memory and near-memory architectures, as well as algorithmic approaches. Here we leverage the low-power and the inherently binary operation of magnetic tunnel junctions (MTJs) to demonstrate neural network hardware inference based on passive arrays of MTJs. In general, transferring a trained network model to hardware for inference is confronted by degradation in performance due to device-to-device variations, write errors, parasitic resistance, and nonidealities in the substrate. To quantify the effect of these hardware realities, we benchmark 300 unique weight matrix solutions of a 2-layer perceptron to classify the Wine dataset for both classification accuracy and write fidelity. Despite device imperfections, we achieve software-equivalent accuracy of up to 95.3 % with proper tuning of network parameters in 15 x 15 MTJ arrays having a range of device sizes. The success of this tuning process shows that new metrics are needed to characterize the performance and quality of networks reproduced in mixed signal hardware.