Synapse Compression for Event-Based Convolutional-Neural-Network Accelerators

TL;DR

This paper introduces a hardware-based synapse compression scheme that drastically reduces memory requirements for event-based CNN accelerators, enabling complex neural networks to run efficiently on small neuromorphic chips.

Contribution

It presents a novel lightweight hardware method to compress synaptic memory by thousands of times, facilitating the deployment of CNNs on compact neuromorphic hardware.

Findings

Memory footprint reduced by up to 374x

Implementation cost increased by only 2%

Enables complex CNNs on small neuromorphic chips

Abstract

Manufacturing-viable neuromorphic chips require novel computer architectures to achieve the massively parallel and efficient information processing the brain supports so effortlessly. Emerging event-based architectures are making this dream a reality. However, the large memory requirements for synaptic connectivity are a showstopper for the execution of modern convolutional neural networks (CNNs) on massively parallel, event-based (spiking) architectures. This work overcomes this roadblock by contributing a lightweight hardware scheme to compress the synaptic memory requirements by several thousand times, enabling the execution of complex CNNs on a single chip of small form factor. A silicon implementation in a 12-nm technology shows that the technique increases the system's implementation cost by only 2%, despite achieving a total memory-footprint reduction of up to 374x compared to the best previously published technique.