A Case For Noisy Shallow Gate-Based Circuits In Quantum Machine Learning

TL;DR

This paper investigates how circuit design parameters and noise affect the performance of gate-based quantum circuits in machine learning, providing practical guidelines for near-term quantum hardware.

Contribution

It systematically evaluates the impact of circuit depth, width, and noise on quantum machine learning models, offering design guidelines for NISQ devices.

Findings

Shallow, wide circuits outperform deep ones in noise-free settings.

Certain circuit topologies are more robust to noise for classification tasks.

Guidelines are proposed for designing effective quantum circuits on NISQ hardware.

Abstract

There is increasing interest in the development of gate-based quantum circuits for the training of machine learning models. Yet, little is understood concerning the parameters of circuit design, and the effects of noise and other measurement errors on the performance of quantum machine learning models. In this paper, we explore the practical implications of key circuit design parameters (number of qubits, depth etc.) using several standard machine learning datasets and IBM's Qiskit simulator. In total we evaluate over 6500 unique circuits with $n \approx 120700$ individual runs. We find that in general shallow (low depth) wide (more qubits) circuit topologies tend to outperform deeper ones in settings without noise. We also explore the implications and effects of different notions of noise and discuss circuit topologies that are more / less robust to noise for classification machine learning tasks. Based on the findings we define guidelines for circuit topologies that show near-term promise for the realisation of quantum machine learning algorithms using gate-based NISQ quantum computer.