Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS

TL;DR

This paper introduces a cascode cross-coupled dynamic comparator in 65 nm CMOS that enhances high-speed, high-resolution ADC performance by improving gain and regeneration at small input differences.

Contribution

It presents a novel comparator design that increases differential gain and reduces common-mode voltage, enabling faster operation at small input differences in 65 nm CMOS.

Findings

Achieves 46.5 ps delay at 1 mV input difference

Operates at 1.1 V supply voltage

Outperforms existing comparators in speed and sensitivity

Abstract

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparator performance degrades at small input difference voltages due to a limited pre-amplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is presented. The proposed comparator improves the differential gain of the pre-amplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in 65 nm CMOS technology. The results demonstrate that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.