A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA

TL;DR

This paper presents a flexible FPGA implementation of Hoeffding Trees for real-time machine learning in embedded systems, demonstrating high speed and comparable accuracy to traditional methods.

Contribution

The work introduces a parameterizable HLS-based Hoeffding Tree implementation optimized for FPGA deployment, with detailed resource and performance evaluation.

Findings

Achieves 8.3x faster inference than ARM Cortex-A53 at 103MHz.

Resource requirements vary with feature size and number of classes.

Maintains comparable accuracy to reference implementations on UCI datasets.

Abstract

Decision trees are often preferred when implementing Machine Learning in embedded systems for their simplicity and scalability. Hoeffding Trees are a type of Decision Trees that take advantage of the Hoeffding Bound to allow them to learn patterns in data without having to continuously store the data samples for future reprocessing. This makes them especially suitable for deployment on embedded devices. In this work we highlight the features of an HLS implementation of the Hoeffding Tree. The implementation parameters include the feature size of the samples (D), the number of output classes (K), and the maximum number of nodes to which the tree is allowed to grow (Nd). We target a Xilinx MPSoC ZCU102, and evaluate: the design's resource requirements and clock frequency for different numbers of classes and feature size, the execution time on several synthetic datasets of varying sample sizes (N), number of output classes and the execution time and accuracy for two datasets from UCI. For a problem size of D3, K5, and N40000, a single decision tree operating at 103MHz is capable of 8.3x faster inference than the 1.2GHz ARM Cortex-A53 core. Compared to a reference implementation of the Hoeffding tree, we achieve comparable classification accuracy for the UCI datasets.