A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal

TL;DR

This paper introduces a two-level approximate logic synthesis method that combines cube insertion and removal, significantly reducing literal count and runtime for error-resilient circuit design.

Contribution

It presents a novel synthesis approach that improves scalability and efficiency over existing methods for approximate logic optimization.

Findings

Literal reduction up to 93% at 5% error rate

Runtime improvements over state-of-the-art methods

Effective scalability for large circuits with high error thresholds

Abstract

Approximate computing is an attractive paradigm for reducing the design complexity of error-resilient systems, therefore improving performance and saving power consumption. In this work, we propose a new two-level approximate logic synthesis method based on cube insertion and removal procedures. Experimental results have shown significant literal count and runtime reduction compared to the state-of-the-art approach. The method scalability is illustrated for a high error threshold over large benchmark circuits. The obtained solutions have presented a literal number reduction up to 38%, 56% and 93% with respect to an error rate of 1%, 3% and 5%, respectively.