Hardware Software Co-design framework for Data Encryption in Image Processing Systems for the Internet of Things Environmen

TL;DR

This paper presents a hardware-software co-design framework for implementing AES-128 encryption on IoT edge devices, optimizing performance and power consumption for image data protection.

Contribution

It introduces a co-simulation framework combining VHDL and software tools for efficient AES encryption in IoT image processing systems.

Findings

FSM architecture outperforms loop unrolled in power and area

Successful hardware emulation on Zedboard and KCU105 platforms

Effective encryption and decryption of biomedical images demonstrated

Abstract

Data protection is a severe constraint in the heterogeneous IoT era. This article presents a Hardware-Software Co-Simulation of AES-128 bit encryption and decryption for IoT Edge devices using the Xilinx System Generator (XSG). VHDL implementation of AES-128 bit algorithm is done with ECB and CTR mode using loop unrolled and FSM-based architecture. It is found that AES-CTR and FSM architecture performance is better than loop unrolled architecture with lesser power consumption and area. For performing the Hardware-Software Co-Simulation on Zedboard and Kintex-Ultra scale KCU105 Evaluation Platform, Xilinx Vivado 2016.2 and MATLAB 2015b is used. Hardware emulation is done for grey images successfully. To give a practical example of the usage of proposed framework, we have applied it for Biomedical Images (CTScan Image) as a case study. Security analysis in terms of the histogram, correlation, information entropy analysis, and keyspace analysis using exhaustive search and key sensitivity tests is also done to encrypt and decrypt images successfully.