Testability-Aware Low Power Controller Design with Evolutionary Learning
Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu

TL;DR
This paper introduces a testability-aware low power controller using evolutionary learning, which adaptively optimizes XORNet-based scan control to improve fault coverage and reduce testing time.
Contribution
It proposes a genetic algorithm-based method to generate XORNets that adaptively control scan chains, enhancing encoding capacity and test efficiency.
Findings
Fault coverage improved by up to 2.11% with the new method.
Testing time decreased by up to 47.09%.
Reduced control bits without sacrificing coverage.
Abstract
XORNet-based low power controller is a popular technique to reduce circuit transitions in scan-based testing. However, existing solutions construct the XORNet evenly for scan chain control, and it may result in sub-optimal solutions without any design guidance. In this paper, we propose a novel testability-aware low power controller with evolutionary learning. The XORNet generated from the proposed genetic algorithm (GA) enables adaptive control for scan chains according to their usages, thereby significantly improving XORNet encoding capacity, reducing the number of failure cases with ATPG and decreasing test data volume. Experimental results indicate that under the same control bits, our GA-guided XORNet design can improve the fault coverage by up to 2.11%. The proposed GA-guided XORNets also allows reducing the number of control bits, and the total testing time decreases by 20.78% on…
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · VLSI and FPGA Design Techniques
