Design of Many-Core Big Little \mu Brain for Energy-Efficient Embedded Neuromorphic Computing
M. Lakshmi Varshika, Adarsha Balaji, Federico Corradi, Anup Das, Jan, Stuijt, Francky Catthoor

TL;DR
This paper presents a scalable many-core neuromorphic hardware design called rain, featuring heterogeneous cores and a specialized software framework, SentryOS, to efficiently accelerate spiking deep CNN inference in energy-constrained embedded systems.
Contribution
It introduces a novel big little rain hardware architecture with a parallel segmented bus interconnect and a tailored software framework for efficient spiking neural network inference.
Findings
Energy reduction of 37% to 98% across applications
Latency reduction of 9% to 25%
Throughput increase of 20% to 36%
Abstract
As spiking-based deep learning inference applications are increasing in embedded systems, these systems tend to integrate neuromorphic accelerators such as Brain to improve energy efficiency. We propose a Brain-based scalable many-core neuromorphic hardware design to accelerate the computations of spiking deep convolutional neural networks (SDCNNs). To increase energy efficiency, cores are designed to be heterogeneous in terms of their neuron and synapse capacity (big cores have higher capacity than the little ones), and they are interconnected using a parallel segmented bus interconnect, which leads to lower latency and energy compared to a traditional mesh-based Network-on-Chip (NoC). We propose a system software framework called SentryOS to map SDCNN inference applications to the proposed design. SentryOS consists of a compiler and a run-time manager. The compiler compiles…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · CCD and CMOS Imaging Sensors
