Self-Learning Tuning for Post-Silicon Validation

TL;DR

This paper introduces a novel reinforcement learning-based method for post-silicon validation, enabling efficient and robust performance tuning amidst increasing chip complexity.

Contribution

It presents a learn-to-optimize approach using reinforcement learning to address complex, mixed-type tuning tasks in post-silicon validation, surpassing traditional methods.

Findings

Effective tuning of complex chip parameters

Robust performance improvements demonstrated

Enhanced efficiency over existing approaches

Abstract

Increasing complexity of modern chips makes design validation more difficult. Existing approaches are not able anymore to cope with the complexity of tasks such as robust performance tuning in post-silicon validation. Therefore, we propose a novel approach based on learn-to-optimize and reinforcement learning in order to solve complex and mixed-type tuning tasks in a efficient and robust way.