Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding

TL;DR

This paper introduces the RCQ paradigm for low-bit LDPC decoding, enabling efficient, high-performance message passing with reduced storage and computational complexity, and extends it with layered architecture enhancements.

Contribution

It proposes the RCQ framework with dynamic non-uniform quantization, introduces layer-specific RCQ with hierarchical quantization, and demonstrates FPGA implementation benefits.

Findings

RCQ with 4-bit messages outperforms table-lookup methods in FER.

Layer-specific RCQ achieves optimal FER performance.

FPGA implementation reduces resource usage significantly.

Abstract

This paper uses the reconstruction-computation-quantization (RCQ) paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution (DDE). Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding MinSum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ (LS-RCQ), an extension of RCQ decoding for layered architectures. LS-RCQ uses layer-specific message representations to achieve the best possible FER performance. For LS-RCQ, this paper proposes using layered DDE featuring hierarchical dynamic quantization (HDQ) to design LS-RCQ parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered MinSum RCQ decoder with 3-bit messages achieves more than a $10\%$ reduction in LUTs and routed nets and more than a $6\%$ decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset MinSum decoder.