Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks

TL;DR

This paper introduces a GNN-based model to rapidly estimate FPGA accelerator design quality, significantly speeding up the optimization process in high-level synthesis workflows.

Contribution

It presents a novel application of graph neural networks to predict FPGA design quality, enabling faster exploration of design options compared to traditional methods.

Findings

GNN model estimates design quality in milliseconds

High accuracy in quality prediction demonstrated

Accelerates FPGA accelerator optimization process

Abstract

High-level synthesis (HLS) has freed the computer architects from developing their designs in a very low-level language and needing to exactly specify how the data should be transferred in register-level. With the help of HLS, the hardware designers must describe only a high-level behavioral flow of the design. Despite this, it still can take weeks to develop a high-performance architecture mainly because there are many design choices at a higher level that requires more time to explore. It also takes several minutes to hours to get feedback from the HLS tool on the quality of each design candidate. In this paper, we propose to solve this problem by modeling the HLS tool with a graph neural network (GNN) that is trained to be used for a wide range of applications. The experimental results demonstrate that by employing the GNN-based model, we are able to estimate the quality of design in milliseconds with high accuracy which can help us search through the solution space very quickly.