Image Denoising in FPGA using Generic Risk Estimation

TL;DR

This paper presents an efficient FPGA implementation of a generic risk estimator for image denoising that works without assumptions on noise distribution, utilizing undecimated Haar wavelet transforms and parallel architecture for high throughput.

Contribution

The paper introduces a novel FPGA design for generic risk-based image denoising using undecimated Haar wavelets with optimized hardware architecture.

Findings

Achieves 3.5ms processing time for 512x512 images.

Recursive Haar wavelet implementation is more hardware-expensive than direct.

Parallel pipelined architecture enhances throughput and efficiency.

Abstract

The generic risk estimator addresses the problem of denoising images corrupted by additive white noise without placing any restriction on the statistical distribution of the noise. In this paper, we discuss an efficient FPGA implementation of this algorithm. We use the undecimated Haar wavelet transform with shrinkage parameters for each sub-band as the denoising function. The computational complexity and memory requirement of the algorithm is first analyzed. To optimize the performance, a combination of convolution and recursion is employed to realize Haar filter bank and gradient descent algorithm is used to find the shrinkage parameters. A fully pipelined and parallel architecture is developed to achieve high throughput. The proposed design achieves an execution time of 3.5ms for an image of size 512x512. We also show that the recursive implementation of Haar wavelet is more expensive than the direct implementation in terms of hardware utilization.