Silicon Photonic Architecture for Training Deep Neural Networks with Direct Feedback Alignment

TL;DR

This paper presents a silicon photonic architecture enabling on-chip training of deep neural networks using direct feedback alignment, achieving high speed and energy efficiency, demonstrated with MNIST dataset training.

Contribution

Introduces a CMOS-compatible silicon photonic system for neural network training utilizing direct feedback alignment, enabling ultra-fast, energy-efficient on-chip learning.

Findings

Achieves trillions of MAC operations per second.

Consumes less than one picojoule per MAC.

Successfully trains deep neural networks on MNIST.

Abstract

There has been growing interest in using photonic processors for performing neural network inference operations; however, these networks are currently trained using standard digital electronics. Here, we propose on-chip training of neural networks enabled by a CMOS-compatible silicon photonic architecture to harness the potential for massively parallel, efficient, and fast data operations. Our scheme employs the direct feedback alignment training algorithm, which trains neural networks using error feedback rather than error backpropagation, and can operate at speeds of trillions of multiply-accumulate (MAC) operations per second while consuming less than one picojoule per MAC operation. The photonic architecture exploits parallelized matrix-vector multiplications using arrays of microring resonators for processing multi-channel analog signals along single waveguide buses to calculate the gradient vector for each neural network layer in situ. We also experimentally demonstrate training deep neural networks with the MNIST dataset using on-chip MAC operation results. Our novel approach for efficient, ultra-fast neural network training showcases photonics as a promising platform for executing AI applications.