A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning

TL;DR

This paper introduces a silicon photonic-electronic neural chip based on a butterfly architecture that significantly reduces optical component count and energy consumption for deep learning, demonstrating high accuracy in image recognition.

Contribution

The work presents a novel optical subspace neural network architecture and a compact butterfly-style neural chip that lowers optical component usage and improves efficiency over traditional GEMM-based ONNs.

Findings

Achieved 94.16% accuracy in handwritten digit recognition.

Reduced optical component count by up to 7x compared to GEMM-based ONNs.

Demonstrated robustness with 3-bit weight programming precision.

Abstract

The optical neural network (ONN) is a promising hardware platform for next-generation neurocomputing due to its high parallelism, low latency, and low energy consumption. Previous ONN architectures are mainly designed for general matrix multiplication (GEMM), leading to unnecessarily large area cost and high control complexity. Here, we move beyond classical GEMM-based ONNs and propose an optical subspace neural network (OSNN) architecture, which trades the universality of weight representation for lower optical component usage, area cost, and energy consumption. We devise a butterfly-style photonic-electronic neural chip to implement our OSNN with up to 7x fewer trainable optical components compared to GEMM-based ONNs. Additionally, a hardware-aware training framework is provided to minimize the required device programming precision, lessen the chip area, and boost the noise robustness. We experimentally demonstrate the utility of our neural chip in practical image recognition tasks, showing that a measured accuracy of 94.16% can be achieved in hand-written digit recognition tasks with 3-bit weight programming precision.