Brain-inspired Cognition in Next Generation Racetrack Memories
Asif Ali Khan, Sebastien Ollivier, Stephen Longofono, Gerald Hempel,, Jeronimo Castrillon, Alex K. Jones

TL;DR
This paper introduces a novel racetrack memory-based architecture for hyperdimensional computing, enabling efficient in-memory cognition tasks with significant improvements in speed and energy efficiency.
Contribution
It presents a new RTM-based in-memory HDC architecture with minimal CMOS overhead, leveraging transverse read operations for accelerated cognition processing.
Findings
7.8x faster runtime than FPGA implementation
5.3x lower energy consumption than FPGA
8.6x energy reduction compared to existing in-memory systems
Abstract
Hyperdimensional computing (HDC) is an emerging computational framework inspired by the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike conventional computational frameworks that operate on numbers, HDC, like the brain, uses high dimensional random vectors and is capable of one-shot learning. HDC is based on a well-defined set of arithmetic operations and is highly error-resilient. The core operations of HDC manipulate HD vectors in bulk bit-wise fashion, offering many opportunities to leverage parallelism. Unfortunately, on conventional Von-Neuman architectures, the continuous movement of HD vectors among the processor and the memory can make the cognition task prohibitively slow and energy-intensive. Hardware accelerators only marginally improve related metrics. On the contrary, only partial implementation of an HDC framework inside memory,…
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