A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures

TL;DR

This paper introduces a customizable RISC-V vector architecture simulator and a new benchmark suite for evaluating vector processors across various applications and scenarios, facilitating research and design.

Contribution

It extends the gem5 simulator to support RISC-V vector instructions and presents a novel, versatile benchmark suite for vector architecture research.

Findings

The extended gem5 supports RISC-V vector execution.

The benchmark suite covers diverse application domains.

The study demonstrates the suite's effectiveness in different vector design scenarios.

Abstract

Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that includes a flexible and customizable vector architecture model. In consequence, researchers have to develop their own simulation platform to test their ideas, which consume much research time. However, once the base simulator platform is developed, another question is the following: Which applications should be tested to perform the experiments? The lack of Vectorized Benchmark Suites is another limitation. To face these problems, this work presents a set of tools for designing and evaluating vector architectures. First, the gem5 simulator was extended to support the execution of RISC-V Vector instructions by adding a parameterizable Vector Architecture model for designers to evaluate different approaches according to the target they pursue. Second, a novel Vectorized Benchmark Suite is presented: a collection composed of seven data-parallel applications from different domains that can be classified according to the modules that are stressed in the vector architecture. Finally, a study of the Vectorized Benchmark Suite executing on the gem5-based Vector Architecture model is highlighted. This suite is the first in its category that covers the different possible usage scenarios that may occur within different vector architecture designs such as embedded systems, mainly focused on short vectors, or High-Performance-Computing (HPC), usually designed for large vectors.