Design and implementation of an out-of-order execution engine of floating-point arithmetic operations

TL;DR

This paper presents the hardware design and FPGA implementation of an out-of-order execution engine for floating-point operations, focusing on low power, efficiency, and IEEE-754 compliance for the Lagarto II core.

Contribution

It introduces two FPGA-based out-of-order floating-point execution engines, with the second offering improved area, performance, and energy efficiency.

Findings

Second design with FMAC units outperforms first in efficiency

Supports double-precision and denormalized numbers

Achieves low power consumption in FPGA implementation

Abstract

In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out-of-order execution engine of floating-point arithmetic operations for the Lagarto II core. A first proposal covers the design of a low power consumption issue queue for out-of-order processors, register bank, bypass network, and the functional units for addition/subtraction, multiplication, division/reciprocal, and Fused Multiply Accumulate (FMAC) confirming with the IEEE-754 standard. The design supports double-precision format and denormalized numbers; A second proposal is based on a pair of FMAC as functional units which can perform almost all Floating-point operations, this design is more beneficial in area, performance, and energy efficiency compared with the first version.