Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process

TL;DR

This paper introduces a hierarchical Gaussian process model for wafer-level RF IC performance prediction that accounts for site-to-site variation, significantly reducing measurement costs and improving accuracy in multi-site testing.

Contribution

It presents a novel hierarchical Gaussian process approach that models site-to-site variation and an active sampling method to minimize measurements in wafer testing.

Findings

Reduced estimation error to 1/19 of conventional methods

Decreased measurement count by 97% with maintained accuracy

Effectively models site-to-site variation in RF IC testing

Abstract

Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.