Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed

TL;DR

This paper presents a new quantum programming environment for ion trap testbeds using QCOR, with multi-level optimizations that improve circuit fidelity and reduce native gate counts, facilitating more efficient quantum computations.

Contribution

It introduces a QCOR/XACC backend for ion trap hardware and demonstrates multi-level optimizations that enhance circuit efficiency and fidelity over previous methods.

Findings

Maintains the number of two-qubit native operations on current hardware.

Reduces single-qubit native operations by 1.54 times on current hardware.

Projected hardware upgrades show reductions of 2.40 times in two-qubit and 6.13 times in one-qubit native operations.

Abstract

Ion trap quantum hardware promises to provide a computational advantage over classical computing for specific problem spaces while also providing an alternative hardware implementation path to cryogenic quantum systems as typified by IBM's quantum hardware. However, programming ion trap systems currently requires both strategies to mitigate high levels of noise and also tools to ease the challenge of programming these systems with pulse- or gate-level operations. This work focuses on improving the state-of-the-art for quantum programming of ion trap testbeds through the use of a quantum language specification, QCOR, and by demonstrating multi-level optimizations at the language, intermediate representation, and hardware backend levels. We implement a new QCOR/XACC backend to target a general ion trap testbed and then demonstrate the usage of multi-level optimizations to improve circuit fidelity and to reduce gate count. These techniques include the usage of a backend-specific numerical optimizer and physical gate optimizations to minimize the number of native instructions sent to the hardware. We evaluate our compiler backend using several QCOR benchmark programs, finding that on present testbed hardware, our compiler backend maintains the number of two-qubit native operations but decreases the number of single-qubit native operations by 1.54 times compared to the previous compiler regime. For projected testbed hardware upgrades, our compiler sees a reduction in two-qubit native operations by 2.40 times and one-qubit native operations by 6.13 times.