Xar-Trek: Run-time Execution Migration among FPGAs and Heterogeneous-ISA CPUs

TL;DR

Xar-Trek enables dynamic run-time migration of application functions between heterogeneous CPUs and FPGAs, improving performance and energy efficiency in datacenter servers by leveraging a novel compiler and scheduling framework.

Contribution

It introduces Xar-Trek, a framework that allows dynamic migration of application functions across heterogeneous-ISA CPUs and FPGAs, overcoming static FPGA acceleration limitations.

Findings

Achieves up to 88% performance gains over no-migration baselines.

Develops a heuristic scheduling policy based on workload profiles.

Demonstrates effective migration in a heterogeneous datacenter system.

Abstract

Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant performance and energy gains, with relatively little programmer effort. However, FPGAs have often been overlooked in that context: hardware acceleration using FPGAs involves statically implementing select application functions, which prohibits dynamic and transparent migration. We present Xar-Trek, a new compiler and run-time software framework that overcomes this limitation. Xar-Trek compiles an application for several CPU ISAs and select application functions for acceleration on an FPGA, allowing execution migration between heterogeneous-ISA CPUs and FPGAs at run-time. Xar-Trek's run-time monitors server workloads and migrates application functions to an FPGA or to heterogeneous-ISA CPUs based on a scheduling policy. We develop a heuristic policy that uses application workload profiles to make scheduling decisions. Our evaluations conducted on a system with x86-64 server CPUs, ARM64 server CPUs, and an Alveo accelerator card reveal 88%-1% performance gains over no-migration baselines.