Exploring eFPGA-based Redaction for IP Protection

TL;DR

This paper investigates the practical trade-offs and security implications of using eFPGA-based redaction to protect digital IPs, focusing on area, timing, and security considerations through a case study.

Contribution

It provides a detailed case study analyzing the trade-offs and security aspects of eFPGA redaction for IP protection, using an open-source FPGA fabric generation flow.

Findings

Redacting different modules impacts area and timing overheads.

Certain parts of eFPGA contribute more significantly to security.

Feasibility of eFPGA redaction depends on design trade-offs.

Abstract

Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabrication. However, when deciding which parts of a design to redact, there are a number of practical issues that designers need to consider, including area and timing overheads, as well as security factors. Adapting an open-source FPGA fabric generation flow, we perform a case study to explore the trade-offs when redacting different modules of open-source intellectual property blocks (IPs) and explore how different parts of an eFPGA contribute to the security. We provide new insights into the feasibility and challenges of using eFPGA-based redaction as a security solution.