Evaluation of $SU(3)$ smearing on FPGA accelerator cards

TL;DR

This paper evaluates the performance benefits and challenges of implementing $SU(3)$ gauge field smearing routines on FPGA accelerator cards, specifically Xilinx Alveo U280, for Lattice QCD calculations.

Contribution

It provides an analysis of the feasibility and performance implications of porting $SU(3)$ smearing routines to FPGA accelerators using Vitis, highlighting potential advantages and limitations.

Findings

Benchmarks show performance gains on FPGA cards.

Analysis discusses pros and cons of FPGA implementation.

Insights into FPGA suitability for Lattice QCD routines.

Abstract

Recent FPGA accelerator cards promise large acceleration factors for some specific computational tasks. In the context of Lattice QCD calculations, we investigate the possible gain of moving the $SU(3)$ gauge field smearing routine to such accelerators. We study Xilinx Alveo U280 cards and use the associated Vitis high-level synthesis framework. We discuss the possible pros and cons of such a solution based on the gathered benchmarks.