A SVD-Based Synchrophasor Estimator for P-class PMUs with Improved Immune from Interharmonic Tones

TL;DR

This paper proposes a novel SVD-based synchrophasor estimator for P-class PMUs that significantly improves robustness against interharmonic tones, ensuring more accurate power system measurements under interference.

Contribution

It introduces an SVD-enhanced least squares algorithm with optimized FIR filters for better interharmonic rejection in P-class PMUs.

Findings

Effective rejection of interharmonic tones demonstrated in tests

Improved estimation accuracy with short time windows

Low computational burden achieved

Abstract

The increasing use of renewable generation, power electronic devices, and nonlinear loads in power systems brings more severe interharmonic tones to the measurand, which can increase estimation errors of P-class PMUs, cause misoperation of protection relays, and even threaten the stability of the power systems. Therefore, the performance of the P-class synchrophasor estimator under interharmonic interference should be evaluated and new estimation schemes that can improve the operational robustness are needed for various protection and control applications. In this paper, a synchrophasor estimator design for P-class PMUs that introduces singular value decomposition to the least square algorithm based on the Taylor series is proposed. By constructing an optimization with proposed adjustable parameters, finite impulse response filters with high transition band attenuation are designed. Numerical and experimental tests verify the proposed dynamic synchrophasor estimator performance and show an effective improvement in rejecting interharmonic tones, especially when a short time window and light computational burden are required.