Design Technology Co-Optimization for Neuromorphic Computing

TL;DR

This paper analyzes the tradeoffs in designing neuromorphic hardware with NVMs, focusing on how process scaling affects endurance and lifetime, and proposes a design flow to enhance inference longevity.

Contribution

It introduces a detailed design-technology tradeoff analysis for neuromorphic hardware, highlighting the impact of scaling on endurance and proposing a method to improve inference lifetime.

Findings

Scaling negatively impacts NVM read endurance.

Inference lifetime depends on synaptic resistance states and parasitic voltage variations.

A design flow can significantly improve inference lifetime.

Abstract

We present a design-technology tradeoff analysis in implementing machine-learning inference on the processing cores of a Non-Volatile Memory (NVM)-based many-core neuromorphic hardware. Through detailed circuit-level simulations for scaled process technology nodes, we show the negative impact of design scaling on read endurance of NVMs, which directly impacts their inference lifetime. At a finer granularity, the inference lifetime of a core depends on 1) the resistance state of synaptic weights programmed on the core (design) and 2) the voltage variation inside the core that is introduced by the parasitic components on current paths (technology). We show that such design and technology characteristics can be incorporated in a design flow to significantly improve the inference lifetime.