Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

TL;DR

This paper presents a hardware architecture for layered decoders of PLDPC-Hadamard codes, achieving high throughput and low error rates on FPGA implementations, advancing decoding efficiency for near-Shannon-limit codes.

Contribution

It introduces a novel hardware architecture with pipelined structures for PLDPC-HC layered decoders, optimizing latency and throughput on FPGA.

Findings

Achieved 1.48 Gbps throughput with BER of 10^-5 at -0.40 dB Eb/N0.

Reduced throughput to 0.20 Gbps at -1.14 dB Eb/N0 with same BER.

Proposed architecture effectively balances latency and throughput for PLDPC-HC decoding.

Abstract

Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist mainly of random address memories, Hadamard sub-decoders and control logics. Two types of pipelined structures are presented and the latency and throughput of these two structures are derived. Implementation of the decoder design on an FPGA board shows that a throughput of $1.48$ Gbps is achieved with a bit error rate (BER) of $10^{-5}$ at around $E_b/N_0 = - 0.40$ dB. The decoder can also achieve the same BER at $E_b/N_0 = - 1.14$ dB with a reduced throughput of $0.20$ Gbps.