An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising

TL;DR

This paper presents an FPGA-based fully pipelined bilateral grid system for real-time image denoising that efficiently handles variable window sizes, outperforming existing methods in speed and resource usage.

Contribution

It introduces a novel FPGA implementation of a bilateral grid with variable window size capability, reducing hardware resource increase during larger window processing.

Findings

Suppresses hardware resource increase with larger windows

Achieves real-time denoising of high-resolution images

Outperforms existing designs in speed and resource efficiency

Abstract

The bilateral filter (BF) is widely used in image processing because it can perform denoising while preserving edges. It has disadvantages in that it is nonlinear, and its computational complexity and hardware resources are directly proportional to its window size. Thus far, several approximation methods and hardware implementations have been proposed to solve these problems. However, processing large-scale and high-resolution images in real time under severe hardware resource constraints remains a challenge. This paper proposes a real-time image denoising system that uses an FPGA based on the bilateral grid (BG). In the BG, a 2D image consisting of x- and y-axes is projected onto a 3D space called a "grid," which consists of axes that correlate to the x-component, y-component, and intensity value of the input image. This grid is then blurred using the Gaussian filter, and the output image is generated by interpolating the grid. Although it is possible to change the window size in the BF, it is impossible to change it on the input image in the BG. This makes it difficult to associate the BG with the BF and to obtain the property of suppressing the increase in hardware resources when the window radius is enlarged. This study demonstrates that a BG with a variable-sized window can be realized by introducing the window radius parameter wherein the window radius on the grid is always 1. We then implement this BG on an FPGA in a fully pipelined manner. Further, we verify that our design suppresses the increase in hardware resources even when the window size is enlarged and outperforms the existing designs in terms of computation speed and hardware resources.