From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

TL;DR

This paper explores a middle ground between FPGA and ASIC implementations for obfuscating integrated circuits, balancing security, area, power, and performance using a custom CAD tool and physical synthesis in 65nm technology.

Contribution

It introduces a novel FPGA-ASIC design space exploration method with a compatible CAD flow for obfuscated circuits, supported by physical layouts and security analysis.

Findings

Obfuscated circuits can be effectively implemented in 65nm technology.

Security depends on circuit resemblance to FPGA structures.

Trade-offs between security and performance are demonstrated.

Abstract

Threats associated with the untrusted fabrication of integrated circuits (ICs) are numerous: piracy, overproduction, reverse engineering, hardware trojans, etc. The use of reconfigurable elements (i.e., look-up tables as in FPGAs) is a known obfuscation technique. In the extreme case, when the circuit is entirely implemented as an FPGA, no information is revealed to the adversary but at a high cost in area, power, and performance. In the opposite extreme, when the same circuit is implemented as an ASIC, best-in-class performance is obtained but security is compromised. This paper investigates an intermediate solution between these two. Our results are supported by a custom CAD tool that explores this FPGA-ASIC design space and enables a standard-cell based physical synthesis flow that is flexible and compatible with current design practices. Layouts are presented for obfuscated circuits in a 65nm commercial technology, demonstrating the attained obfuscation both graphically and quantitatively. Furthermore, our security analysis revealed that for truly hiding the circuit's intent (not only portions of its structure), the obfuscated design also has to chiefly resemble an FPGA: only some small amount of logic can be made static for an adversary to remain unaware of what the circuit does.