A Deep Learning Inference Scheme Based on Pipelined Matrix Multiplication Acceleration Design and Non-uniform Quantization

TL;DR

This paper presents a low-power FPGA-based MLP accelerator that uses pipelined matrix multiplication and non-uniform quantization to improve performance and reduce power consumption in edge computing deep learning inference.

Contribution

It introduces a novel FPGA implementation of a pipelined matrix multiplication scheme combined with non-uniform quantization for efficient deep learning inference.

Findings

Achieves better performance on handwritten digit classification and Q-learning tasks.

Reduces power consumption compared to existing methods.

Demonstrates effectiveness of non-uniform quantization in FPGA accelerators.

Abstract

Matrix multiplication is the bedrock in Deep Learning inference application. When it comes to hardware acceleration on edge computing devices, matrix multiplication often takes up a great majority of the time. To achieve better performance in edge computing, we introduce a low-power Multi-layer Perceptron (MLP) accelerator based on a pipelined matrix multiplication scheme and a nonuniform quantization methodology. The implementation is running on Field-programmable Gate Array (FPGA) devices and tested its performance on handwritten digit classification and Q-learning tasks. Results show that our method can achieve better performance with fewer power consumption.