An early shutdown circuit for power reduction in high-precision dynamic comparators

TL;DR

This paper introduces an early shutdown circuit and offset cancellation technique for high-precision dynamic comparators, significantly reducing power consumption while maintaining speed and accuracy in low-power ADC applications.

Contribution

It proposes a novel early shutdown approach combined with time domain offset cancellation, enhancing power efficiency in dynamic comparators without sacrificing performance.

Findings

Power consumption reduced by 21.7% in worst case

Circuit consumes 47μW at 500MHz

Residual offset standard deviation is 620μV

Abstract

Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators directly affects the overall power consumption and effective number of bits of the ADC. In this paper, an early shutdown approach is proposed to deactivate the first stage preamplifier at the suitable time. Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects. With the proposed method power consumption can be reduced in low power high precision dynamic comparators. The proposed method has been simulated in a standard 0.18{\mu}m CMOS technology and the results confirm its effectiveness. The proposed circuit has the ability of reducing the power consumption by 21.7% in the worst case, while having little effect on the speed and accuracy in comparison with the conventional methods. The proposed comparator consumes only 47{\mu}W while operating at 500MHz. Furthermore, Monte Carlo evaluations showed that the standard deviation of the residual input referred offset was 620{\mu}V.