Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware
Juan G\'omez-Luna, Izzat El Hajj, Ivan Fernandez, Christina Giannoula,, Geraldo F. Oliveira, Onur Mutlu

TL;DR
This paper analyzes the first real-world processing-in-memory (PIM) architecture by UPMEM, highlighting its performance, workload suitability, and design insights for future PIM systems, addressing the memory bottleneck in modern workloads.
Contribution
It provides the first comprehensive analysis of UPMEM's real-world PIM architecture, offering practical insights and recommendations for hardware and software design.
Findings
UPMEM PIM architecture effectively reduces data movement overhead.
Workload characteristics influence PIM system performance.
Guidelines for optimizing software and hardware for PIM systems.
Abstract
Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bound workloads is insufficient to amortize the cost of memory access. Fundamentally addressing this data movement bottleneck requires a paradigm where the memory system assumes an active role in computing by integrating processing capabilities. This paradigm is known as processing-in-memory (PIM). Recent research explores different forms of PIM architectures, motivated by the emergence of new technologies that integrate memory with a logic layer, where processing elements can be easily placed. Past works…
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Taxonomy
TopicsAdvanced Data Storage Technologies · Parallel Computing and Optimization Techniques · Advanced Memory and Neural Computing
