RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems

TL;DR

This paper presents an ASIC implementation of a RED-based scheduler for mixed-criticality real-time systems, enabling efficient scheduling of diverse process criticalities with higher CPU utilization.

Contribution

It introduces a novel on-chip RED-based scheduler design that supports mixed-criticality processes, improving flexibility and resource utilization over traditional EDF-based schedulers.

Findings

Supports mixed-criticality process scheduling

Achieves higher CPU utilization

Handles diverse process deadlines and criticalities

Abstract

Real-time embedded systems that combine processes of various criticalities (i.e. mixed-criticality real-time systems) represent an emerging research that faces many issues. This paper describes a new ASIC design of a coprocessor that realizes process scheduling for mixed-criticality real-time systems. The solution proposed in this paper uses Robust Earliest Deadline (RED) algorithm. Due to the on-chip implementation of the scheduler, all scheduler operations always take two clock cycles to execute. The proposed solution was verified by simulations that applied millions of random inputs. Chip area costs are evaluated by synthesis into ASIC using 28 nm TSMC technology. The proposed RED-based scheduler is compared with an existing EDF-based scheduler that supports hard real-time processes only. Even though the RED-based scheduler costs more chip area, it can handle any combinations of process criticalities, variations of process execution times and deadlines, achieves higher CPU utilization and can be used for scheduling of non-real-time, soft real-time and hard real-time processes combined within one system.