Numerical model for 32-bit magnonic ripple carry adder

TL;DR

This paper presents a numerical model for a 32-bit magnonic ripple carry adder, demonstrating its design, simulation, and energy efficiency, with potential for scalable magnonic circuit applications.

Contribution

It introduces a computation model for magnonic circuits, enabling complex circuit design and simulation, and analyzes energy consumption and signal regeneration requirements.

Findings

The 32-bit magnonic adder can operate with as low as 961aJ per operation.

Additional regenerators are necessary for signal normalization between half-adders.

Benchmarking shows potential for scalable, energy-efficient magnonic circuits.

Abstract

In CMOS-based electronics, the most straightforward way to implement a summation operation is to use the ripple carry adder (RCA). Magnonics, the field of science concerned with data processing by spin-waves and their quanta magnons, recently proposed a magnonic half-adder that can be considered as the simplest magnonic integrated circuit. Here, we develop a computation model for the magnonic basic blocks to enable the design and simulation of magnonic gates and magnonic circuits of arbitrary complexity and demonstrate its functionality on the example of a 32-bit integrated RCA. It is shown that the RCA requires the utilization of additional regenerators based on magnonic directional couplers with embedded amplifiers to normalize the magnon signals in-between the half-adders. The benchmarking of large-scale magnonic integrated circuits is performed. The energy consumption of 30 nm-based magnonic 32-bit adder can be as low as 961aJ per operation with taking into account all required amplifiers.