Superior Resistance Switching in Monolayer MoS2 Channel Based Gated Binary Resistive RAM via Gate-Bias Dependence and a Unique Forming Process

TL;DR

This study investigates the resistive switching behavior in monolayer MoS2-based gated RRAM, revealing how gate bias and electrical stress influence performance, and proposes a forming process to enhance switching reliability.

Contribution

It uncovers the gate-bias dependence of resistive switching in MoS2 RRAM and introduces a novel forming process to improve device performance and reliability.

Findings

Resistive switching is significantly affected by gate voltage and charge conduction.

Electrical stress can induce multiple resistance states similar to synaptic behavior.

A specific electrical stress condition improves switching performance through a forming process.

Abstract

In this work, we unveil the effect of RS, induced by a current-voltage hysteresis cycles across CVD-grown monolayer MoS2 based gated RRAM, on its transistors electrical and reliability characteristics. A unique gate voltage dependence on the RS is identified which has a remarkable impact on the switching performance of MoS2 RRAM. RS behavior was found to be significantly dependent on the charge conduction in the channel. Moreover, we have shown a potential device forming event when MoS2 gated RRAMs were subjected to a steady-state electrical stress. Both hysteresis and steady state electrical stress were found to disturb the transistor action of these gated RRAMs, which in fact can be used as a signature of RS. Interestingly, current-voltage hysteresis resulted in unipolar RS, whereas steady-state electrical stress before RS measurement led to bipolar RS. Moreover, successive stress cycles of such an electrical stress leads to multiple resistance states, a behavior similar to synaptic properties like long-term potentiation and long-term depression, typically found in memristors. We find that charge transport mechanism dominant in the MoS2 FET in conjunction with steady-state stress induced device forming determine the extent of RS induced in these MoS2 based gated RRAMs. Finally on the basis of insights developed from the dependence on charge transport mechanism and steady-state stress induced forming of MoS2 channel, we propose a certain steady-state electrical stress condition which can be used as a forming process employed prior to use of MoS2 based binary RRAMs for improved switching performance.